1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more particularly, to the elimination of a variation between cell rows with respect to the load capacity of each cell in a semiconductor integrated circuit device.
2. Description of the Related Art
A prior art example of a semiconductor integrated circuit having a plurality of cell rows is shown in FIG. 1.
In FIG. 1, the numeral 10 indicates a chip body, 11A through 11D cell rows each comprising a plurality of standard cells, 12 microcell block, 13A through 13D signal amplifying cells provided in respective cell rows 11A through 11D and located in a line in the direction perpendicular to the cell rows, that is, in the vertical direction on the figure. 14A through 14D are signal amplifiers provided in respective signal amplifying cells 13A through 13D, and 15 is a cell-column wiring layer which is thicker in width than a standard wiring layer formed in the circuit, and which interconnects the inputs of the signal amplifying cells 13A through 13D of the cell rows 11A through 11D.
Numeral 16 indicates I/O (input/output) cells located on the periphery of the chip body, and 16A a clock driver cell acting as an input of a clock signal. The clock signal amplified by the cell 16A is supplied to the inputs of the signal amplifiers 14A through 14D of the signal amplifying cells 13A through 13D.
Outputs of the signal amplifying cells 13A through 13D, that is, outputs of the signal amplifiers 14A through 14D, are connected via respective cell-row wiring layers 17A through 17D to a circuit (not shown), for example, a flip flop circuit, in a standard cell (not shown) in the respective cell rows 11A through 11D. The cell-row wiring layers are of a width of the standard wiring layer formed in the circuit.
In the semiconductor integrated circuit device described above, there is a variation between cell rows 11A through 11D with respect to the load capacity (marked with "x" in FIG. 1) of each cell row. The load capacity marked with "x" corresponds to the gate capacity of, for example, a flip flop circuit (not shown) in the standard cell. There is also a variation between the cell rows with respect to the length of the cell-row wiring layer. These variations cause a clock skew in which the output clock signals of the signal amplifying cells in the cell rows have a phase difference between the cell rows 11A through 11D. A smaller clock skew is preferable. However, the clock skew increases by increased size of circuit, increased load capacity, its variation and the like.